In order to make semiconductor devices finer and the operating speed thereof higher, it is proposed to use a multi-layer wiring structure such that multiple layers of wiring, especially metal wiring are stacked and wiring of an upper layer and wiring of a lower layer are electrically interconnected through a via hole formed in an insulating interlayer layer. Typically in such a multi-layer wiring, via holes are tapered and side walls of the via holes are sloped as disclosed, for example, in "Next Generation Ultra LSI Process Technique", published by Realize Inc. on Apr. 30, 1988, pp 238-241, in order to assure continuity of wiring at steps of via holes, i.e., step coverage and avoid breakage of wiring.
If wiring of an upper layer and wiring of a lower layer are made of the same material, such as Al, and a via hole has a diameter larger than the width of the wiring of the upper layer, then wiring of the lower layer would be simultaneously etched at the time of etching the wiring of the upper layer for patterning. Conventionally, therefore, it is necessary to make the size of each via hole smaller than the width of wiring of the upper layer. As semiconductor devices become finer and the width of wiring becomes narrower, therefore, the size of via hole has become smaller.
On the other hand, the thickness of insulating interlayer is required to be at least 0.6 .mu.m in order to assure interlayer insulation and suppress increase of the capacitance between upper and lower wiring. Therefore, the aspect ratio of the via hole becomes large. As a result, it becomes difficult to form the via hole with a taper. Even if the via hole is formed with a taper, the step coverage of wiring of the upper layer in the via hole is reduced. The conventional multi-layer wiring structure, therefore, does not have high reliability.